1. Field
Exemplary embodiments of the present invention relate to semiconductor design technologies, and more particularly, to a synchronous semiconductor memory device that supports varying preamble periods of a data strobe signal.
2. Description of the Related Art
In general, semiconductor memory devices including DRAM receive write data from a chip set (for example, a memory controller) and transmits read data to the chip set. Meanwhile, in the case of a synchronous semiconductor memory device, both of a chip set and a memory are operated in synchronization with a system clock. However, when data are transmitted to the semiconductor memory device from the chip set, the data and the system clock have different loads and traces, and a skew occurs between the data and the system clock due to a positional difference between the system clock and a plurality of memories.
In order to reduce such a skew between the data and the system clock, the chip set transmits a data strobe signal DQS together with data, when the chip set transmits the data to a memory. The data strobe signal DQS is called an echo clock, and has the same load and trace as data. Therefore, when the memory strobes data using the data strobe signal DQS, a skew occurring due to a positional difference between the system clock and the memory is minimized/reduced. Meanwhile, during a read operation, the memory transmits data and a read strobe signal DQS to the chip set.
Meanwhile, the data strobe signal DQS has a preamble period announcing the beginning of data transmission one period (1tCK) before data is inputted. For example, the data strobe signal DQS starts to toggle in a high impedance (Hi-Z) state or changes to a logic low level in a preamble period.
FIG. 1 is a block diagram illustrating a write path of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device 100 includes a command input unit 101, a command decoder 103, an address input unit 105, a column address generation unit 107, an address decoder 109, a strobe command generation unit 111, a data input unit 113, a data alignment unit 115, a data driving unit 117, a write driving unit 119, and a core unit 121.
The command input unit 101 is configured to receive external commands RAS#, CAS#, and WE#. The command decoder 103 is configured to decode the commands inputted through the command input unit 101 and generate first and second internal commands CASP10YA and CASPWT.
The address input unit 105 is configured to receive external addresses A0 to Ak. The column address generation unit 107 is configured to generate column addresses AY0 to AYk corresponding to the addresses inputted through the address input unit 105, in response to the first internal command CASP10YA. The address decoder 109 is configured to generate a write enable signal BWEN and a column select signal YI in response to the column addresses AY0 to AYk.
The strobe command generation unit 111 is configured to generate first and second data alignment control commands CASPWT_LOAD_DQS1 and CASPWT_LOAD_DQS2 by synchronizing the second internal command CASPWT with an internal data strobe signal IDQS_WT in response to first and second burst length information BL4 and BL8, and generate a data driving control command CASPWT_LOAD_CLK by synchronizing the second internal command CASPWT with an internal clock signal ICLK_WT.
The data input unit 113 is configured to receive external data DIN. The data alignment unit 115 is configured to align the data inputted through the data input unit 113 in response to the first and second data alignment control commands CASPWT_LOAD_DQS1 and CASPWT_LOAD_DQS2. The data driving unit 117 is configured to transmit aligned data DIN_ALGN outputted from the data alignment unit 115 to a global input/output line GIO in response to the data driving control command CASPWT_LOAD_CLK.
The write driving unit 119 is configured to output data DIN_GIO transmitted through the global input/output line GIO in response to the write enable signal BWEN. The core unit 121 is configured to store the data outputted from the write driving unit 119 in response to the column select signal YI.
Hereafter, an operation of the conventional semiconductor memory device 100 will be described with reference to FIG. 2.
FIG. 2 is a timing diagram illustrating the operation of the conventional semiconductor memory device 100.
Referring to FIG. 2, the external data DIN having a burst length of ‘8’ are inputted through the data input unit 113 in synchronization with rising and falling edges of the internal data strobe signal IDQS_WT.
Subsequently, the command decoder 103 generates the first and second internal commands CASP10YA and CASPWT corresponding to the external commands RAS#, CAS#, and WE#.
According to an example, the strobe command generation unit 111 outputs the first and second data alignment control commands CASPWT_LOAD_DQS1 and CASPWT_LOAD_DQS2 by synchronizing the second internal command CASPWT with the internal data strobe signal IDQS_WT and outputs the data driving control command CASPWT_LOAD_CLK by synchronizing the second internal command CASPWT with the internal clock signal ICLK_WT. At this time, it can be seen that the first and second data alignment control commands CASPWT_LOAD_DQS1 and CASPWT_LOAD_DQS2 belong to a data strobe signal domain (DQS domain), and the data driving control command CASPWT_LOAD_CLK belongs to a clock signal domain (CLK domain). The data alignment unit 115 first aligns four data R1, F1, R0, and F0 according to the falling edges of the first data alignment control command CASPWT_LOAD_DQS1, and subsequently aligns the other four data R3, F3, R2, and F2 according to the falling edges of the second data alignment control command CASPWT_LOAD_DQS2. In such a state, the data driving unit 117 transmits the aligned data DIN_ALGN through the global input/output line GIO according to rising edges of the data driving control command CASPWT_LOAD_CLK.
Meanwhile, the column address generation unit 107 generates the column addresses AY0 to AYk corresponding to the external addresses A0 to Ak in response to the first internal command CASP10YA, and the address decoder 109 generates the write enable signal BWEN and the column select signal YI according to the column addresses AY0 to AYk.
Accordingly, the write driving unit 119 transmits the data loaded in the global input/output line GIO to the core unit 121 in response to the write enable signal BWEN, and the core unit 121 stores the data transmitted from the write driving unit 119 in a corresponding memory cell (not illustrated) through a bit lines sense amplifier BLSA, in response to the column select signal YI.
However, the semiconductor memory device 100 having the above-described configuration has the following features.
First, a domain crossing margin tDQSS of data will be described briefly before the features of the conventional semiconductor memory device 100 is explained. The domain crossing margin tDQSS of data refers to a permissible range of a skew which occurs between the internal data strobe signal IDQS_WT and the internal clock signal ICLK_WT and may be variously defined according to the specification. Meanwhile, next-generation semiconductor memory devices operating at high speed support a preamble period of the internal data strobe signal IDQS_WT that varies depending on different high speed operations. Accordingly, the data domain crossing margin tDQSS is applied in various manners, according to the varying preamble period of the internal data strobe signal IDQS_WT.
The domain crossing margin tDQSS of the data, which is applied in various manners according to the varying preamble period of the internal data strobe signal IDQS_WT, is to comply with the specification. However, it is not easy to apply the conventional semiconductor memory device 100 so that it supports the varying preamble period of the internal data strobe signal IDQS_WT. In other words, the domain crossing margin tDQSS of data between the second data alignment control command CASPT_LOAD_DQS2 generated from the DQS domain and the data driving control command CASPWT_LOAD_CLK generated from the CLK domain may be differently set depending on the preamble period, because the specification of the domain crossing margin tDQSS of data differs according to the preamble period of the varying internal data strobe signal IDQS_WT, even though the domain crossing margin tDQSS of the data is to comply with the specification. For example, in a mode where the preamble period supports two cycles (2tCK) of the internal data strobe signal IDQS_WT, the specification of the domain crossing margin tDQSS of the data increases two times more than in a mode where the supported preamble period is equal to one cycle (1tCK) of the internal data strobe signal IDQS_WT. In order to satisfy the specification, the domain crossing margin tDQSS of the data between the second data alignment control command CASPWT_LOAD_DQS2 and the data driving control command CASPWT_LOAD_CLK may be set to a larger value.
Therefore, the output timings of some command signals which are generated during a write operation are to be controlled, in order to satisfy the domain crossing margin tDQSS of the data which is applied in various manners according to the varying preamble period of the internal data strobe signal IDQS_WT.